The present invention relates to the field of logic devices, and the systems and methods for programming the same. Logic devices are electronic devices that are adapted to process data. Logic devices can be designed by specifying transistors or other switching devices and their connections to form individual logic gates that provide the desired functions. Logic devices can also be created by adapting a user design to standardized device architectures, such as structured ASICs (application-specific integrated circuits), standard cell architectures, and programmable devices.
Programmable devices, such as FPGAs (field-programmable gate arrays), typically include thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform logic operations. Programmable devices also include a number of functional blocks having specialized logic devices adapted to a specific logic operations. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
A typical design cycle for determining the configuration of a programmable device, referred to as compilation, starts with an extraction phase, followed by a logic synthesis phase, a technology-mapping phase, a fitting phase (which can include clustering, placement, and routing), and an assembly phase. The extraction and synthesis phases take a user design, typically expressed in a hardware description language such as Verilog or VHDL (very-high-speed integrated circuit hardware description language), and produce a set of logic gates implementing the user design. In the technology-mapping phase, the set of logic gates is permutated over the hardware architecture of the programmable device in order to match elements of the user design with corresponding types of elements of the programmable device. The clustering, placement, and routing phases assign the various portions of the user design to specific logic cells and functional blocks and determine the configuration of the configurable switching circuit used to route signals between these logic cells and functional blocks, taking care to satisfy the user timing constraints as well as possible. In the assembly phase, a configuration file defining the programmable device configuration is created. The configuration can then be loaded into a programmable device to implement the user design.
To meet performance targets, timing constraints are specified for user designs. Long-path timing constraints specify the maximum amount of delay permitted in the various portions of the user design. If a long-path timing constraint is violated, a signal will not arrive at its intended destination in time and the user design may malfunction. Short-path timing constraints specify the minimum amount of delay permitted in the various portions of the user design. If a short-path timing constraint is violated, a signal arrives at its destination too early, potentially overwriting the previous value at the destination before it can be processed. Timing constraints can be specified by designers or automatically generated based upon general performance requirements of a user design. Additionally, designers using more sophisticated design techniques can specify some timing constraints to control specific aspects of the user design implementation, such as clock skew. All logic designs are subject to similar timing constraints regardless of the logic device implementation style used (custom logic, standard cells, structured ASICs, programmable devices, etc.). Consequently, most design timing optimization techniques are applicable to all implementation styles and although the invention will be discussed primarily with reference to programmable devices, it is equally applicable to all logic implementation styles.
Due to manufacturing variations, the performance capabilities of logic devices may vary from device to device. Furthermore, different operating conditions, for example due to temperatures and voltage variations, can also affect the performance capabilities of logic devices. To cope with these and other causes of variation, each set of performance capabilities of a logic device is modeled by a process/operating condition corner (sometimes referred to as a timing corner or a corner). Each corner represents the set of timing delays for the various portions of the logic device. Additionally, performance capabilities can vary within each logic device, for example due to manufacturing variations, rise/fall signal delay differences, and operating condition variations; these variations are sometimes referred to as intra-corner variations. Therefore, each corner can include a range of timing delays for each portion of the logic device.
To ensure that a user design operates correctly when implemented, the user design must be implemented so as to satisfy both long-path and short-path timing constraints. However, typical compilation tools only optimize user designs to satisfy long-path timing constraints. Designers must then manually modify and re-optimize their designs to satisfy short-path timing constraints.
Additionally, user designs must be verified to operate correctly when implemented, despite the performance variability of individual devices due to manufacturing and operating condition variations. Unfortunately, typical compilation tools cannot simultaneously optimize a user design for multiple corners. Instead, compilation tools optimize user designs for a single corner; designers must then manually optimize user designs for additional corners. Furthermore, typical compilation tools cannot take into account the variability of performance capabilities within a logic device.
Therefore, a system and method that optimizes user designs to satisfy both long-path and short-path timing constraints is desirable. It is further desirable for the system and method to simultaneously optimize user designs for multiple process corners, and operating conditions, and to take into account the variability of performance capabilities within a logic device. It is also desirable for the system and method to be implemented in one or more stages of the compilation process. Additionally, it is desirable for the system and method to integrate easily with previous single-corner compilation methods.